FPSIM(3E)

NAME
fpsim - floating-point simulation

DESCRIPTION
This system provides for software emulation of floating-point instructions if floating-point hardware is not present. The kernel code in question simulates an FP11 floating-point processor by intercepting illegal-instruction traps and decoding and interpreting the floating-point opcodes.

HISTORY
This simulator is derived from Bell's, which used signal(2) and was compiled into the user program. Mike Tilson of HCR thought of and did the original kernel-mode simulator; this improved variant by Henry Spencer.

BUGS
The floating-point status register is incompletely supported; only the float/double mode, int/long mode, and condition-code bits work. Other bits read and write properly but have no effect. In particular, there are no traps except for invalid opcode.

Divide by zero is not detected.

Rounding mode is not supported.

The presence of -0 is not noticed or trapped.

The STST instruction is not supported (it is in any event impossible to support properly in a multiprogramming system), and the error registers don't exist.

Long-int conversions with the long int in registers don't work.

Certain valid but bizarre combinations of opcode and addressing mode/register are treated as illegal opcodes.

Roundoff errors probably don't match any existing FP11.

Behavior at extremes of the number range is suspect.

Checking for segmentation violations etc. is sloppy; an error will probably result but it may be delayed.

Compared to a real FP11, it's excruciatingly slow.